sample_hold_gate

Sample & Hold and Gate
Author:
License: GPL
Github: jls/logic/sample_hold_gate.axo

Inlets

bool32.rising trigger

frac32.bipolar input

Outlets

bool32 positive value gate

bool32 negative value gate

frac32.bipolar output

Declaration
int ntrig;
int tmp;
Init
ntrig = 0;
tmp = 0;
Control Rate
if ((inlet_trig > 0) && !ntrig) {

  ntrig = 1;

  tmp = inlet_in;

} else if (!(inlet_trig > 0))
  ntrig = 0;

if (tmp > 0)
  outlet_pos = 1;
else
  outlet_pos = 0;
if (tmp < 0)
  outlet_neg = 1;
else
  outlet_neg = 0;

outlet_out = tmp;

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