Akso - Audio DSP Platform

smplr

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edits a bank of samples recorded with 'smplr'. 'slot' sets the slot to work on, 'copy','move' and 'delete' have to be triggered via 'trig'. 'defrag' will clear unused sample data and compact the referred table. 'clear' will clear the data.

Author: Robert Schirmer

License: BSD

Github: rbrt/smplr/smplr.axo

IO Variants: 2

Variant: 1

Inlets

bool32.rising trig

bool32.rising copy

bool32.rising move

bool32.rising delete

bool32.rising defragment the sample data

bool32.rising clear all data

int32.positive slot to work on

Outlets

bool32.pulse pulse on delete

Attributes

objref wave

Declaration

static const uint32_t LENGTHPOW = 12;
static const uint32_t LENGTH = 1 << 12;
static const uint32_t LENGTHMASK = (1 << 12) - 1;
static const uint32_t BITS = 32;
static const uint32_t GAIN = 0;
uint32_t *array;
#define WAVE attr_wave.array
#define W_GAIN attr_wave.GAIN
#define W_LENGTH attr_wave.LENGTH

uint32_t global[16];
#define GLOBAL global
#define REC_HEAD global[15]
#define TEMPO global[0]

uint32_t *del_array;
uint16_t delcount;

bool REC;
uint8_t RECSLOT;
uint8_t SHIFT;

bool dtrig;
bool clrtrig;
uint8_t mslot;
uint8_t srcslot;
bool defragtrig;
bool move;
bool cpytemptrig;
bool mtrig;
bool trig;

int32_t paramtemp[32];

void delete_slot(uint8_t target) __attribute__((noinline)) {
  uint16_t adr = target << 5;
  int check = 1;
  if (array[adr + 30]) {
    int start = array[adr + 28];
    int end = array[adr + 29];
    memset(&array[adr], 0, 128);
    int i;
    for (i = 0; i < 127; i++)
      if (array[(i << 5) + 29] == end)
        check = 0;
    if (check) {
      del_array[delcount] = start;
      del_array[delcount + 1] = end;
      delcount += 2;
    }
  }
}

void defrag() __attribute__((noinline)) {
  int i;
  for (i = 0; i < delcount; i += 2) {
    int start = del_array[i];
    int end = del_array[i + 1];
    int length = (end - start);
    int shift_index;
    for (shift_index = 0; shift_index < LENGTH; shift_index += 32)
      if (array[shift_index + 28] >= end) {
        array[shift_index + 28] -= length;
        array[shift_index + 29] -= length;
      }
    int move_samples;
    for (move_samples = end; move_samples < REC_HEAD; move_samples++)
      WAVE[move_samples - length] = WAVE[move_samples];
    int shift_chunks;
    for (shift_chunks = 0; shift_chunks < delcount; shift_chunks += 2)
      if (del_array[shift_chunks] >= end) {
        del_array[shift_chunks] -= length;
        del_array[shift_chunks + 1] -= length;
      }
    REC_HEAD -= length;
  }
  delcount = 0;
}

Init

static uint32_t _array[attr_poly][LENGTH] __attribute__((section(".sdram")));
array = &_array[parent->polyIndex][0];

{
  int i;
  for (i = 0; i < LENGTH; i++)
    array[i] = 0;
}

static uint32_t _del_array[attr_poly][512] __attribute__((section(".sdram")));
del_array = &_del_array[parent->polyIndex][0];

{
  int i;
  for (i = 0; i < 512; i++)
    del_array[i] = 0;
}

SHIFT = (27 - attr_wave.LENGTHPOW);

Control Rate

mslot = inlet_slot % 128;
outlet_delete = 0;

// delete
if (inlet_delete && !dtrig) {
  delete_slot(mslot);
  dtrig = 1;
  outlet_delete = 1;
}

// defrag
if (inlet_defrag && !defragtrig) {
  defragtrig = 1;
  defrag();
}

// paste
if ((inlet_trig && !trig) && cpytemptrig && (inlet_copy || move)) {
  trig = 1;
  delete_slot(mslot);
  memcpy(&array[mslot << 5], &paramtemp[0], 128);
  if (move) {
    delete_slot(srcslot);
    outlet_delete = 1;
    move = 0;
  }
}

// copy
if ((inlet_trig && !trig) && !cpytemptrig && (inlet_copy || move)) {
  trig = 1;
  cpytemptrig = 1;
  srcslot = mslot;
  memcpy(&paramtemp[0], &array[mslot << 5], 128);
}

// move
if (inlet_move && !mtrig) {
  mtrig = 1;
  move = 1;
}

// clear
if (inlet_clear && !clrtrig) {
  clrtrig = 1;
  delcount = 0;
  REC_HEAD = 0;
  int i;
  for (i = 0; i < LENGTH; i++)
    array[i] = 0;
}

if (!inlet_copy && !inlet_move)
  cpytemptrig = 0;
if (!inlet_move) {
  mtrig = 0;
  move = 0;
}
if (!inlet_clear)
  clrtrig = 0;
if (!inlet_defrag)
  defragtrig = 0;
if (!inlet_trig)
  trig = 0;
if (!inlet_delete)
  dtrig = 0;

Variant: 2