multi3
64 different logic functions for 3 inputs! 4th mode samples logic outcome at rising edge, but updates output after the rising edge->eg. for generative logic feedback networks
Inlets
bool32 input 1
bool32 input 2
bool32 i3
bool32 trg
int32 logic mode: 0=AND,1=NAND,2=OR,3=NOR,4=XOR,5=XNOR,6=S&H,7=T&H
int32 update mode: 0=direct,1=when i1 changes,2=when i2 changes,3=when either one changes,4=when trg input goes high
Outlets
bool32 output
Parameters
int32 logic mode: 0=AND,1=NAND,2=OR,3=NOR,4=XOR,5=XNOR,6=S&H,7=T&H. Selector works as an offset, outcome is wrapped within list size
int32 update mode: 0=direct,1=when i1 changes,2=when i2 changes,3=when either one changes. Selector works as an offset, outcome is wrapped within list size
Displays
bool32 o1
int bt, bit, p1, p2, O, trg, s, S, mode;int upd = inlet_update + param_update % 5;
switch (upd) {
case 0:
mode = inlet_mode + param_mode;
break; // direct update
case 1:
if (!(p1 == inlet_i1)) // update when i1 changes
{
mode = inlet_mode + param_mode;
}
break;
case 2:
if (!(p2 == inlet_i2)) // update when i2 changes
{
mode = inlet_mode + param_mode;
}
break;
case 3:
if ((!(p1 == inlet_i1)) ||
(!(p2 == inlet_i2))) // update when either i1 or i2 changes
{
mode = inlet_mode + param_mode;
}
break;
case 4:
mode = inlet_mode + param_mode;
break; // update triggered by trg input
}
p1 = inlet_i1;
p2 = inlet_i2;
int o, tp;
switch (mode < 32 ? mode & 31 : ((mode - 32) & 7)) {
case 0:
o = (inlet_i1) && (inlet_i2);
break; // AND12
case 1:
o = !((inlet_i1) && (inlet_i2));
break; // NAND12
case 2:
o = ((inlet_i1) || (inlet_i2));
break; // OR12
case 3:
o = !((inlet_i1) || (inlet_i2));
break; // NOR12
case 4:
o = !((inlet_i1) == (inlet_i2));
break; // XOR12
case 5:
o = ((inlet_i1) == (inlet_i2));
break; // XNOR12
case 6:
if (inlet_i2 && !bt) {
bt = 1;
bit = inlet_i1;
} else if (bt && !inlet_i2) {
bt = 0;
}
o = bit;
break; // sample&hold bit12
case 7:
if (inlet_i2) {
bit = inlet_i1;
}
o = bit;
break; // track&hold bit12
case 8:
o = (inlet_i1) && (inlet_i3);
break; // AND13
case 9:
o = !((inlet_i1) && (inlet_i3));
break; // NAND13
case 10:
o = ((inlet_i1) || (inlet_i3));
break; // OR13
case 11:
o = !((inlet_i1) || (inlet_i3));
break; // NOR13
case 12:
o = !((inlet_i1) == (inlet_i3));
break; // XOR13
case 13:
o = ((inlet_i1) == (inlet_i3));
break; // XNOR13
case 14:
if (inlet_i3 && !bt) {
bt = 1;
bit = inlet_i1;
} else if (bt && !inlet_i3) {
bt = 0;
}
o = bit;
break; // sample&hold bit13
case 15:
if (inlet_i3) {
bit = inlet_i1;
}
o = bit;
break; // track&hold bit13
case 16:
o = (inlet_i2) && (inlet_i3);
break; // AND23
case 17:
o = !((inlet_i2) && (inlet_i3));
break; // NAND23
case 18:
o = ((inlet_i2) || (inlet_i3));
break; // OR23
case 19:
o = !((inlet_i2) || (inlet_i3));
break; // NOR23
case 20:
o = !((inlet_i2) == (inlet_i3));
break; // XOR23
case 21:
o = ((inlet_i2) == (inlet_i3));
break; // XNOR23
case 22:
if (inlet_i3 && !bt) {
bt = 1;
bit = inlet_i2;
} else if (bt && !inlet_i3) {
bt = 0;
}
o = bit;
break; // sample&hold bit23
case 23:
if (inlet_i3) {
bit = inlet_i2;
}
o = bit;
break; // track&hold bit23
case 24:
o = (inlet_i1) && (inlet_i2) && (inlet_i3);
break; // AND123
case 25:
o = !((inlet_i1) && (inlet_i2) && (inlet_i3));
break; // NAND123
case 26:
o = ((inlet_i1) || (inlet_i2) || (inlet_i3));
break; // OR123
case 27:
o = !((inlet_i1) || (inlet_i2) || (inlet_i3));
break; // NOR123
case 28:
tp = inlet_i1 + inlet_i2 + inlet_i3;
o = !((tp == 0) || (tp == 2));
break; // XOR123 (if either one or two are high)
case 29:
tp = inlet_i1 + inlet_i2 + inlet_i3;
o = ((tp == 0) || (tp == 2));
break; // XNOR123 (only if all high or all low)
case 30:
tp = inlet_i1 + inlet_i2 + inlet_i3;
o = (tp == 1);
break; // only if one is high
case 31:
tp = inlet_i1 + inlet_i2 + inlet_i3;
o = (tp == 2);
break; // only if two are high
}
if (mode > 31) {
switch (((mode - 32) >> 3) &
3) // more combinations could be added, keep in mind to change the &3
// into %"amount of cases" eg. %8
{
case 0:
O = inlet_i3 && o;
break; // AND with result of i1 and i2
case 1:
O = inlet_i3 > 0 ? 0 : o;
break; // NAND with result of i1 and i2
case 2:
O = inlet_i3 > 0 ? !o : o;
break; // invert result of i1 and i2
case 3:
if (inlet_i3) {
O = o;
}
break; // T&H result of i1 and i2
}
} else {
O = o;
}
if (upd == 4) {
S = s;
if (inlet_trg && !trg) {
trg = 1;
s = O;
} else if (trg && !inlet_trg) {
trg = 0;
}
} else {
S = O;
}
outlet_o = S;
disp_o1 = S;