fm4op_alg

Based on drj/Are Leistad drj/switch/fm4op_alg - FM 4 op algorithm router ala TX81Z, WITHOUT feedback path on all leaf operators - Algorithm selected by integer input starting at zero - no output saturation (one can use a separate antialiased saturator)
Author: Smashed Transistors based on Are Leistad work
License: BSD
Github: tiar/mux/fm4op_alg.axo

Inlets

frac32buffer Op 1 input

frac32buffer OP 2 input

frac32buffer OP 3 input

frac32buffer OP 4 input

int32 algorithm

Outlets

frac32buffer Op 1 output

frac32buffer Op 2 output

frac32buffer Op 3 output

frac32buffer Output

Control Rate
int32_t j;
/*
 *  TX81Z algorithms:
 *  1: op4 -> op3 -> op2 -> op1
 *  2: (op4 + op3) -> op2 -> op1
 *  3: op3 -> op2 + op4 -> op1
 *  4: op4 -> op3 + op2 -> op1
 *  5: (op2 -> op1) + (op4 -> op3)
 *  6: (op4 -> op1) + (op4 -> op2) + op4 -> op3)
 *  7: op1 + op2 + (op4 -> op3)
 *  8: op1 + op2 + op3 + op4
 */
switch (inlet_algorithm) {
case 0:
  // 1: op4 -> op3 -> op2 -> op1
  for (j = 0; j < BUFSIZE; ++j) {
    outlet_op1o[j] = inlet_op2i[j];
    outlet_op2o[j] = inlet_op3i[j];
    outlet_op3o[j] = inlet_op4i[j];
    outlet_out[j] = inlet_op1i[j];
  }
  break;
case 1:
  // 2: (op4 + op3) -> op2 -> op1
  for (j = 0; j < BUFSIZE; ++j) {
    outlet_op1o[j] = inlet_op2i[j];
    outlet_op2o[j] = inlet_op3i[j] + inlet_op4i[j];
    outlet_op3o[j] = 0;
    outlet_out[j] = inlet_op1i[j];
  }
  break;
case 2:
  // 3: op3 -> op2 + op4 -> op1
  for (j = 0; j < BUFSIZE; ++j) {
    outlet_op1o[j] = inlet_op2i[j] + inlet_op4i[j];
    outlet_op2o[j] = inlet_op3i[j];
    outlet_op3o[j] = 0;
    outlet_out[j] = inlet_op1i[j];
  }
  break;
case 3:
  // 4: op4 -> op3 + op2 -> op1
  for (j = 0; j < BUFSIZE; ++j) {
    outlet_op1o[j] = inlet_op2i[j] + inlet_op3i[j];
    outlet_op2o[j] = 0;
    outlet_op3o[j] = inlet_op4i[j];
    outlet_out[j] = inlet_op1i[j];
  }
  break;
case 4:
  // 5: (op2 -> op1) + (op4 -> op3)
  for (j = 0; j < BUFSIZE; ++j) {
    outlet_op1o[j] = inlet_op2i[j];
    outlet_op2o[j] = 0;
    outlet_op3o[j] = inlet_op4i[j];
    outlet_out[j] = inlet_op1i[j] + inlet_op3i[j];
  }
  break;
case 5:
  // 6: (op4 -> op1) + (op4 -> op2) + (op4 -> op3)
  for (j = 0; j < BUFSIZE; ++j) {
    outlet_op1o[j] = inlet_op4i[j];
    outlet_op2o[j] = inlet_op4i[j];
    outlet_op3o[j] = inlet_op4i[j];
    outlet_out[j] = inlet_op1i[j] + inlet_op2i[j] + inlet_op3i[j];
  }
  break;
case 6:
  // 7: op1 + op2 + (op4 -> op3)
  for (j = 0; j < BUFSIZE; ++j) {
    outlet_op1o[j] = 0;
    outlet_op2o[j] = 0;
    outlet_op3o[j] = inlet_op4i[j];
    outlet_out[j] = inlet_op1i[j] + inlet_op2i[j] + inlet_op3i[j];
  }
  break;
case 7:
  // 8: op1 + op2 + op3 + op4
  for (j = 0; j < BUFSIZE; ++j) {
    outlet_op1o[j] = 0;
    outlet_op2o[j] = 0;
    outlet_op3o[j] = 0;
    outlet_out[j] =
        inlet_op1i[j] + inlet_op2i[j] + inlet_op3i[j] + inlet_op4i[j];
  }
  break;
}

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